AI Agent UpdateIntel says it is only a few percent behind TSMC on tech — but catching its scale will be slow
Intel says it is nearly level with TSMC on chip technology. The catch, by its own admission, is the factory floor — and that gap closes slowly.
The News
Intel's technology chief has given the company's most candid progress report in years — and it cuts both ways. Chief technology officer Pushkar Ranade, speaking on the Dwarkesh podcast, said Intel is only a few percentage points behind TSMC on performance, power or area density, the three measures that define how good a chip manufacturing process is. That is a confident claim from a company that spent years trailing its Taiwanese rival. But Ranade paired it with a frank concession: catching TSMC's wafer scale will take time and sustained investment.
Scale, in plain terms, is how many chips a factory can crank out. TSMC does not just make leading-edge chips; it makes them in enormous volumes, reliably, for the world's biggest customers. Intel can close a technology gap with a better process, but closing a volume gap means building fabs, qualifying them with customers, and proving yields — the share of chips that come off the line working — over many quarters. Ranade's message is that the first gap is nearly closed and the second is a long grind.
Intel vice president Chris Auth added a technical plank to the argument. Backside power delivery, he said, relaxes the requirements on how tightly patterns must be packed on the front side of the chip, letting Intel print with High NA EUV directly. And 14A — Intel's next process generation — is already an option in the process design kit, the toolkit chip designers use to build on a process, handled customer by customer. In other words, Intel is not just promising a future process; it says customers can already start designing on it.
Nearly level on technology, still climbing on scale — Intel's own progress report cuts both ways.
Why It Matters
To judge this story, you need to separate two different races that are often confused. The first is the technology race: can you print smaller, faster, more efficient transistors? Intel says it is now within a few percentage points of TSMC there, which would end a decade in which it trailed badly. The second is the manufacturing race: can you make those transistors by the millions, at high yield, on schedule, for demanding customers? That race is measured in factories and quarters, not breakthroughs, and Intel concedes it is still behind.
The High NA EUV choice sits at the intersection of both races. EUV machines use extreme-ultraviolet light to etch chip patterns, and High NA is the sharpest, most expensive generation yet. Betting on it directly is bold: if it works as Intel claims, backside power delivery gives it room to work, and Intel leapfrogs a generation of tooling. If yields disappoint or costs balloon, the bet becomes a very expensive lesson. Either way, it is a decision whose payoff will be visible in factory results, not in interviews.
For investors, the honest frame is this: TSM is the comparator here, not a company reporting an event, and INTC is the company asking to be believed. Intel's technology claims are now specific enough to check, which is progress. But a chip business is ultimately judged on shipped volume, and volume is exactly what Intel says will take time. That is why the verdict is Mixed rather than Bullish: the direction looks right, the distance is still real.
Analyst's Take
Read this as Mixed, because both halves of Intel's story are believable at the same time. The technology framing is genuinely encouraging: a few percentage points on performance, power or density is a gap a customer can live with, especially if Intel competes on price or capacity. The backside-power argument and 14A's availability in the design kit are concrete, checkable claims, not vague promises. If designers are actually building on 14A, that is real momentum.
But the scale concession is the part that should temper enthusiasm. TSMC's advantage is not a single breakthrough; it is years of volume, yield learning and customer trust, and none of that transfers overnight. The test for Intel is not what its executives say on a podcast but what its fabs deliver: yields, on-time shipments and repeat orders at volume. Until those arrive, this is a credible comeback story with an unproven ending. Readers' poll: is Intel's scale gap a two-year problem or a five-year problem?
By The Numbers
FAQ
What is wafer scale, in plain terms?
A wafer is a thin silicon disc that chips are printed on, and wafer scale means how many wafers — and therefore how many chips — a factory can crank out. A company can have a brilliant chip design, but if it cannot make enough of them, customers will go elsewhere. Scale is about volume, reliability and cost, not just cleverness.
What is EUV, and what makes High NA EUV special?
EUV stands for extreme ultraviolet lithography: machines that use extremely short-wavelength light to etch microscopically fine patterns onto silicon wafers. High NA EUV is the newest generation of these machines, with sharper optics that can print finer features. They are enormously expensive, which is why choosing the right machine generation is a multi-billion-dollar bet.
What is backside power delivery?
Traditionally, a chip gets its power through wires on the same side as its signal connections, which crowds the layout. Backside power delivery moves the power wires to the underside of the chip, freeing space on the front. Intel's argument is that this extra room relaxes how tightly the front-side patterns must be packed, making High NA EUV a more direct fit for its process.
Source: WCCFTech